1. Field of the Invention
The present invention is directed in general to word line faults in memories. In one aspect, the present invention relates to address fault detection for integrated circuit memories and associated methods of operation.
2. Description of the Related Art
Integrated circuit memories may fail in a variety of ways, and memory failures can have bigger impact as memories are increasingly used in various computer systems and applications. There are a variety of different ways for a memory to fail, including address decoder faults, word line faults, pre-decoder faults, address latch faults. In the class of memory failures relating to operation of the word lines, one type of fault (called a “no word line select” fault) occurs when no word line is enabled when the memory is intended to be accessed. Detection for this type of failure is commonly indicated by a signal called “word line on indicator” which indicates whether a word line has been enabled, i.e., a word line is on. Another type of fault (called a “multiple word line select” fault) occurs when more than one word line is enabled in the same array. Yet another type of fault (called a “false word line select” fault) occurs when a word line in an array is incorrectly asserted while another word line is incorrectly deasserted. Depending on the cause, such faults can be transient or non-transient in nature. For example, transient address faults can be caused by a particle strike in an address decoder, while non-transient address faults can be caused by a physical defect in the memory hardware. Although it is preferable that such errors do not occur, it is often the case that the integrated circuit can continue to function even with such errors, provided that a fault indication is quickly and efficiently provided so that the integrated circuit can make an appropriate correction. Existing memory systems have used address ROM banks with fault detection logic to provide a mechanism for detection of selected transient address faults during functional operation, such as by encoding the address ROM banks with hard encoded word line address information which is used to check if the correct word line is asserted. However, address ROM banks require significant chip area, especially when using a multi-bank array architecture with multiple different word lines since every bank needs a ROM bank.